open-source process design kits (PDKs)
Open-source process design kits (PDKs) refers to the kits containing a set of files, libraries, and documentation that are openly available and provide essential information and resources for designing integrated circuits (ICs) or chips. These kits typically include technology files, device models, layout rules, and other design parameters necessary for designing ICs using a specific semiconductor fabrication process. By being open-source, these PDKs promote accessibility, collaboration, and innovation in IC design by allowing designers to freely access, modify, and redistribute the design resources.
Open-source PDKs are available from various wafer foundries, including SkyWater Technology's SKY130 and GlobalFoundries' GF180MCU.
SkyWater SKY130 PDK
Open PDKs is distributed with files that support the Google/SkyWater sky130 open process description Here and also on GitHub github.com:google/skywater-pdk , you'll discover a plethora of valuable information about their available 130nm CMOS process.
Despite belonging to a mature node (which is quite distant from a leading nm-FinFET node), this process offers an extensive array of process options and features. It's perfectly suitable for numerous analog and digital designs, and even RF up to a few GHz.
SKY130 is a mature 180nm-130nm hybrid technology developed by Cypress Semiconductor that has been used for many production parts. SKY130 is now available as a foundry technology through SkyWater Technology Foundry.The technology is the 8th generation SONOS technology node (130nm).
The technology stack consists of;
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5 levels of metal (p - penta)
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Inductor or Inductor-Capable (i)
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Poly resistor (r)
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SONOS shrunken cell (s)
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Supports 10V regulated supply (10R)
This document provides a concise overview of the different mask (GDS) layers, wiring resistance and capacitance, as well as electromigration regulations.
Unlock the Fascinating World of Electronics and Chip Design
Preparing an IC layout for production at a wafer foundry is an intricate process that involves several checks. Once all these checks are successfully completed and the layout, inclusive of pads, seal rings, etc., is finalized, it is forwarded to the foundry, typically in the form of GDS2 or OASIS files.
For the Makercass internship, we are leveraging the services provided by efabless, which offers infrastructure chips such as Caravel (for digital ICs) or Caravel Analog (for analog ICs). These chips come equipped with essential elements like pads, ESD protection, and programming infrastructure. This document provides initial guidance on utilizing these infrastructure chips for tape-out at efabless.
Given the significant cost and time involved in IC fabrication, it's crucial to ensure that the implemented design is error-free. Besides extensive simulation, a formal design review involving multiple engineers is conducted before tape-out. This review meticulously examines the design, layout, simulation results, and other critical aspects. The provided tape-out (TO) checklist consolidates essential considerations for this crucial stage.